The EVAL-1CH2CHSOICEBZ supports single- and dual-channel 

iCoupler? standard data isolators in 8-lead SOIC packages. The 

evaluation board provides a JEDEC standard, 8-lead SOIC_N 

and 8-lead SOIC_W pad layout. This layout supports signal 

distribution, loopback, and loads referenced to the VDDx or 

GNDx planes, as well as optimal bypass capacitance. Signal 

sources can be conducted to the board through header pins or 

through edge mounted SMA connectors (SMA connectors must 

be ordered separately). Screw terminal blocks on the board provide 

power connections. The board includes 0.2 inch header positions 

for compatibility with active probes (probe header pins must be 

ordered separately). 

The evaluation board follows best PCB design practices for 4-layer 

boards, including a full power and ground plane on each side of 

the isolation barrier. No other electromagnetic interference (EMI) 

or noise mitigation design features are included on this board. 

In cases of high speed operation, or when ultralow emissions are 

required, refer to the AN-1109 Application Note for additional 

board layout techniques. IMPORTANT NOTICE. Read this Agreement carefully before downloading or using this IBIS model. BY DOWNLOADING OR USING THIS IBIS MODEL IN ANY WAY YOU ACKNOWLEDGE THAT YOU HAVE READ, UNDERSTAND AND AGREE TO THE TERMS OF THIS AGREEMENT. IF YOU DO NOT AGREE TO THESE TERMS OR IF YOU DO NOT HAVE THE AUTHORITY DESCRIBED BELOW, DO NOT DOWNLOAD THIS IBIS MODEL, DO NOT USE THIS IBIS MODEL IN ANY WAY, AND PROMPTLY DELETE OR DESTROY ANY COPIES OF THIS IBIS MODEL IN YOUR POSSESSION.

If You are entering into this Agreement on behalf of a company or other organization, You represent that You have the authority to bind it to this Agreement and commit funds on its behalf, and the terms "You" and "Your" will refer to that company or organization.

FEATURES 

Access to 2 data channels 

Multiple connection options 

Support for active probes 

Provisions for cable terminations 

Support for printed circuit board (PCB) edge mounted 

coaxial connectors 

Easy configuration 

SUPPORTED iCoupler DEVICES 

Sample iCoupler digital isolators must be ordered separately; 

supported iCoupler devices are as follows: 

ADuM110N 

ADuM120N/ADuM121N 

ADuM210N 

ADuM225N/ADuM226N 

ADuM7240/ADuM7241 

ADuM1200/ADuM1201 

ADuM1210 

ADuM3200/ADuM3201 

ADuM3210/ADuM3211 

ADuM1280/ADuM1281 

GENERAL DESCRIPTION 

The EVAL-1CH2CHSOICEBZ supports single- and dual-channel 

iCoupler? standard data isolators in 8-lead SOIC packages. The 

evaluation board provides a JEDEC standard, 8-lead SOIC_N 

and 8-lead SOIC_W pad layout. This layout supports signal 

distribution, loopback, and loads referenced to the VDDx or 

GNDx planes, as well as optimal bypass capacitance. Signal 

sources can be conducted to the board through header pins or 

through edge mounted SMA connectors (SMA connectors must 

be ordered separately). Screw terminal blocks on the board provide 

power connections. The board includes 0.2 inch header positions 

for compatibility with active probes (probe header pins must be 

ordered separately). 

The evaluation board follows best PCB design practices for 4-layer 

boards, including a full power and ground plane on each side of 

the isolation barrier. No other electromagnetic interference (EMI) 

or noise mitigation design features are included on this board. 

In cases of high speed operation, or when ultralow emissions are 

required, refer to the AN-1109 Application Note for additional 

board layout techniques.